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t r i q u i n t s e m i c o n d u c t o r , i n c . 1 for additional information and latest specifications, see our website: www.triquint.com mixed signal products features ? 1 gs/s conversion rate ? 8-bit resolution ? dc differential non-linearity 1 / 2 lsb (0.2%) ? dc integral non-linearity 1 lsb (0.4%) ? settling time 2 ns to 0.4% (est.) ? spurious-free dynamic range (sfdr) 45 dbc typical ? ecl-compatible inputs ? synchronous blanking input ? 1.3 w power dissipation ? 44-pin multilayer ceramic package or unpackaged die applications ? display generation ? waveform and signal synthesis ? video signal reconstruction blank a5 a6 b6 a7 (msb) b7 multiplexer ecl input buffers blanking logic master latch slave latch v (-5 v) a blank disable v v i v bandgap reference full-scale adjust v clk clk sela blank d0 d4 qblank q0 q4 d5 d6 d7 q5 q6 q7 binary-to-n-of-7 segment encoder s1 s2 s3 s4 s5 s6 s7 qs1 qs7 + i i4 is1 is7 + current-source array 50 50 out v out v b5 b4 blank i0 sense ref b0 a0 a4 gnd gnd ss aa aa ref d q (-5v) (ext. control loop) d blank d0 d4 qblank q0 q4 triquint's TQ6122 gigadac? is a monolithic, 8-bit digital-to-analog converter capable of conversion rates to at least 1000 megasamples/ second. the TQ6122 dac may be used for display generation, waveform and signal synthesis, and video signal reconstruction. the TQ6122 features a 2:1 data mux at the input for ease of interface and offers synchronous blanking capability for maximum ease of use in video applications. it drives complementary 1 v peak-to-peak swings into 50-ohm loads; on-chip 50- ohm reverse terminations provide extremely fast settling time. due to the inherently high speed of triquint's one-micron gate enhancement / depletion-mode gallium arsenide process, the TQ6122 offers guaranteed operation at clock rates of 1000 mhz, with typical room temperature conversion rates of 1.5 gs/s without multiplexing and 1.3 gs/s when using multiplexed inputs. the TQ6122 features output rise and fall times of 500 ps (10% C 90%), symmetric complementary output transitions, and glitch impulse values less than 10 pv/sec. when used for sine wave synthesis, typical spurious and harmonic free dynamic range is 3 45 dbc. the TQ6122 may be retrofitted into designs which currently use triquint's tq6111, 2, 3, 4m dacs with minimal changes to power supply levels and input and output connections. the part is available in a 44-pin ceramic package or as unpackaged die. TQ6122 1 gigasample/sec, 8-bit digital-to-analog converter
TQ6122 2 for additional information and latest specifications, see our website: www.triquint.com specifications table 1. absolute maximum ratings (1,2) symbol description min typ max units a gnd , d gnd analog and digital ground C2 +2 v v ss digital power C7 v v aa analog power C10 v v o , v o ( max ) analog output (1 v f.s.) C2.5 +2.5 v v i ( max ) digital input levels v ss C0.5 +0.5 v i i ( max ) digital input currents C1 +1 ma p d power dissipation 3.0 w t c case backside temperature C65 +135 c t s storage temperature C65 +150 c notes: 1. unless otherwise specified: a gnd = d gnd = 0 v, v ss = v aa = C5 v, v fs = 1 v pkCpk, case temperature = 27 c. 2. exceeding the absolute maximum ratings may damage the device. the value shown for a particular parameter is determined with all other parameters at their nominal values. table 2. dc characteristics (1) symbol description test conditions min. typ. max. unit v aa analog supply note 2 C5.25 C4.75 v i aa v aa current v fs = 1 v pkCpk 50 62 80 ma v ss digital supply note 2 C5.5 C4.5 v i ss v ss current 145 200 265 ma p d power dissipation 0.9 1.3 1.85 w v eclref ecl reference level note 3, figure 1 C1.5 C1.3 C1.1 v i eclref ecl ref. input bias current note 3, figure 1 d v eclref = 0.2 v C5 0 +5 ma r eclref ecl ref. input resistance figure 1 50 w c eclref ecl ref. input capacitance 2 pf v ih ( dc ) data input high (ecl) dc value (v eclref = C1.3 v) C1100 C500 mv v il ( dc ) data input low (ecl) dc value (v eclref = C1.3 v) v tt C1500 mv v clkh ( dc ), clock high input differential clock, note 4 v eclref +0.3 C0.7 v v clkh ( dc ) v clkl ( dc ), clock low input differential clock, note 4 v tt v eclref C0.3 v v clkl ( dc ) i in data, clock input bias current v ih = C800 mv, v il = C1800 mv C25 +25 ua c in data, clock input capacitance in multilayer ceramic package 0.5 pf v out ( max ), maximum absolute output level note 5 +1 v v out ( max ) v out ( min ), minimum absolute output level note 5 C1.5 v v out ( min ) (continued on next page)
TQ6122 3 for additional information and latest specifications, see our website: www.triquint.com mixed signal products v fs full-scale output swing data bits only, 0C0/1C1 input step 0 1 1.125 v pkCpk r l = 50 w load v zs zero-scale offset v fs = 1 v, no external offset, C35 mv v blank_disable = 0 v d dv blank blanking interval blank input = 1, notes 6, 7 9 10.4 12 %v fs v blank_disable blank current disable control blank current on C5 (v aa )v blank current off 0 (a gnd )v v ref v ref input voltage v fs = 1 v peak-to-peak v aa +0.7 v aa +1.0 v aa +1.4 v v fs = 0 v peak-to-peak v aa C1 v v sense v sense output v fs = 1 v peak-to-peak v aa +0.8 v aa +1.1 v i vref v ref input current v ref = v aa +0.65 10 ua v ref = v aa +1.1 1 ma i ref ext. reference current output v fs = 1 v peak-to-peak 2 2.5 5 ma v iref i ref terminal voltage C1.5 +1 v r out , r out v out , v out output resistance 44 50 57 w matching of r out , r out 0.2 2.5 % c out v out , v out output capacitance 0.3 pf resolution 8 bits monotonicity 8 bits dnl differential non-linearity ( 1 / 2 lsb) 0.2 % f.s. inl integral non-linearity ( 1 lsb) 0.4 % f.s. full-scale symmetry v fs = 1 v peak-to-peak, note 8 C4 +4 mv v fs temperature coefficient note 9 notes: 1. unless otherwise specified: v aa = C5v 5%, v ss = C5 v 10%, v tt = C2v 5%, v fs = 1 v pkCpk, t case = 0 to +85 c 2. see the "power supplies, ground and bypassing" section later in this datasheet for discussion of power supplies. 3. the ecl reference input establishes the switching point for the ecl line receivers used at the data, blank, and select inputs. (see figure 1.) i eclref is the current required to change the internal eclref value by about 200 mv. 4. values shown are for differential clock drive, and apply to both clock and clock inputs. for single-ended drive, the high level should be at least (v eclref +0.5) volts, but must not exceed C700 mv. the low level should be (v eclref C0.5) volts, but must not go below v tt , where v tt is the ecl termination voltage (nominal v tt = C2 v). 5. v out ( max ), v out ( max ), v out ( min ), v out ( min ) represent the limits on the absolute output levels, including offset. 6. blanking interval is the voltage change (as a percentage of the full-scale output swing) added to v fs when blank is asserted. 7. the blank disable input turns off the blank current (dv blank = 0) when held at a gnd , and turns it on when pulled to v aa . 8. full-scale symmetry is a measure of the balance between v out and v out . for a full-scale input change (00000000 C> 1111111), the change in v out will match the change in v out to within 4 mv (1 lsb @ 1 v peak-to-peak). 9. the vfs temperature coefficient is determined primarily by the external reference and loop control op amp. table 2. dc characteristics (1) (continued) symbol description test conditions min typ max unit
TQ6122 4 for additional information and latest specifications, see our website: www.triquint.com symbol description test conditions min typ max unit f clk ( max ) maximum clock frequency unmuxed operation 1000 1500 mhz muxed operation 1000 1300 mhz t rclk,data clock, data input rise time 20% to 80% 300 ps t fclk,data clock, data input fall time 20% to 80% 300 ps t wh duration of clock high percentage of clock period 40 50 60 % t wl duration of clock low percentage of clock period 40 50 60 % t setup data, control setup time see figure 7 ps t hold data, control hold time see figure 7 ps t rout output rise time 10% to 90% 300 ps t fout output fall time 10% to 90% 300 ps t settle output settling time within 0.4% of final value 2 ns glitch impulse 10 pv/sec notes: 1. unless otherwise specified: v aa = C5v 5%, v ss = C5 v + 10% , v fs = 1 v pCp, t case = 0 to +85 c, v ecl = C1.3 v, v ih = C0.8 v, v il = C1.8 v 2. applies to packaged parts only. v ih v il v ecl (-1.3 v nominal) v ih v il (min) (max) v ih (max) v ih (min) external ecl reference input i 2 pf ecl input buffers r c 50 w -1.3v (nominal, internal) eclref, eclref 50 w a7, b7 a0, b0 v ss eclref + + 50 w sela blank -5 v figure 2. definition of v ih , v il for data and blank inputs figure 1. ecl reference input equivalent circuit table 3. ac characteristics (1,2)
TQ6122 5 for additional information and latest specifications, see our website: www.triquint.com mixed signal products (b) TQ6122 video dac operation (0.679 v full-scale) blanking current is enabled by connecting blank disable to v aa . input code v out (1) v out (1) full scale 11111111 C0.679 v C0.071 v full scale C 1 lsb 11111110 C0.676 v C0.074 v half scale + 1 lsb 10000001 C0.343 v C0.407 v half scale 10000000 C0.341 v C0.409 v half scale C 1 lsb 01111111 C0.338 v C0.412 v zero scale + 1 lsb 00000001 C0.003 v C0.747 v zero scale 00000000 0.000 v C0.750 v blank = high x . . . . . x C0.750 v 0.000 v input code v out (1) v out (1) full scale 11111111 C0.996 v 0.000 v full scale C 1 lsb 11111110 C0.992 v C0.004 v half scale + 1 lsb 10000001 C0.504 v C0.492 v half scale 10000000 C0.500 v C0.496 v half scale C1 lsb 01111111 C0.496 v C0.500 v zero scale + 1 lsb 00000001 C0.004 v C0.992 v zero scale 00000000 0.000 v C0.996 v figure 3. typical digital input circuit (including clock inputs) 50 50 50 500 500 microstrip input dac input protection network v tt ? v v ss r in, c in to input buffer ? v (a) TQ6122 instrumentation dac operation (1 v full-scale) blanking current is shunted to ground by tying blank disable to a gnd and forcing blank = 0. notes: 1. all values shown for v out and v out assume identical load resistors (rl1 and rl2 in figure 5), and no externally imposed output offset voltage (v os in figure 5). zero-scale offset is ignored. figure 4. v out , v out , and input code relationships for (a) typical instrumentation and (b) video configurations
TQ6122 6 for additional information and latest specifications, see our website: www.triquint.com figure 5. output equivalent circuit, showing terminated 50-ohm transmission line loads figure 6. definition of t wh and t wl t wl(clk) t wh(clk) 50% digital input non-inverting output (v ) inverting output (v ) boundary of dac out i out, r out c 50 r t1 50 r t2 z = 50 0 1000 pf os (see fig. 18) (?v to +4v) v (for no output offset) 50 r l1 50 r l2 0.1uf "far-end" terminations 100 pf out i z = 50 0 out out agnd
TQ6122 7 for additional information and latest specifications, see our website: www.triquint.com mixed signal products figure 7. TQ6122 data and control timing symbol description typical @ 25 c unit t ds data setup time (1) 0ps t dh data hold time (2) +325 ps t ss sela setup time (1,3) +350 ps t sh sela hold time (2,3) C100 ps notes: 1. setup time is defined to be positive for data or control transitions occurring before the negative-going edge of the clock. 2. hold time is defined to be positive for data or control transitions occurring after the negative-going edge of the clock. 3. while sela does not strictly have a setup and hold time, it is convenient to express its allowed transition region limits in these terms. ss t sela data clock sh t dh t ds t
TQ6122 8 for additional information and latest specifications, see our website: www.triquint.com mechanical characteristics the TQ6122 dac is packaged in a proprietary 44-pin multilayer ceramic package which provides high-speed, controlled-impedance interconnects and integral power supply bypassing. the leads are set on 0.050 centers, and are formed for gull-wing surface mounting. figure 8 shows the pinout diagram of the packaged ic as seen from the top, opposite the cavity side; figure 9 lists pin numbers, names and i/o levels. figure 10 illustrates the pertinent dimensions of the package and figure 11 shows the mounting footprint. since the TQ6122 dissipates on the order of 1.3 w, adequate heat sinking is essential for proper operation of the device. figure 12 shows one possible heat sink arrangement based on a multi-finned top hat heat sink available from thermalloy. an environment with a minimum of 100 fpm (feet per minute) of forced air cooling is assumed; >200 fpm is preferred. figure 8. TQ6122 pinout 23 12 11 34 pin 1 vaa iref ecl ref a0 a1 dgnd a2 a3 a4 a5 vss vss clock clock n/c sela dgnd blank b7 b6 b5 vss TQ6122am top view of mlc-44 package as it sits on circuit board (cavity is down) vaa vref vsense blank disable agnd vout vout agnd agnd agnd vss vss a6 a7 dgnd b0 b1 dgnd b2 b3 b4 vss notes: 1. a7, b7 = msb inputs 2. n/c = no internal connection pin signal interface level (typ.) 1 , 11, 12, v ss C5 v 33, 34, 44 2 b5 600 mv pkCpk centered at C1.3 v @ dc 3 b6 600 mv pkCpk centered at C1.3 v @ dc 4 b7 ( msb ) 600 mv pkCpk centered at C1.3 v @ dc 5 blank 600 mv pkCpk centered at C1.3 v @ dc 6, 28, d gnd 0 v 37, 40 7 sela 600 mv pkCpk centered at C1.3 v @ dc 8 no connection 9 clock 1v pkCpk centered at C1.3 v @ ac 10 clock 1v pkCpk centered at C1.3 v @ ac 13C15, 18 a gnd 0 v 16 v out 0 v to C1 v 17 v out C1 v to 0 v 19 blank enable = v aa (i blank = on) disable disable = a gnd (i blank = off) 20 v sense v aa + 0.8, for v fs = 1 v pkCpk figure 9. TQ6122 pin descriptions pin signal interface level (typ.) 21 v ref v aa +1, for v fs = 1v pkCpk 22, 23 v aa C5 v 24 i ref 2.5 ma for v fs = 1v pkCpk 25 ecl ref C1.3 v 26 a0 ( lsb ) 600 mv pkCpk centered at C1.3 v @ dc 27 a1 600 mv pkCpk centered at C1.3 v @ dc 29 a2 600 mv pkCpk centered at C1.3 v @ dc 30 a3 600 mv pkCpk centered at C1.3 v @ dc 31 a4 600 mv pkCpk centered at C1.3 v @ dc 32 a5 600 mv pkCpk centered at C1.3 v @ dc 35 a6 600 mv pkCpk centered at C1.3 v @ dc 36 a7 ( msb ) 600 mv pkCpk centered at C1.3 v @ dc 38 b0 ( lsb ) 600 mv pkCpk centered at C1.3 v @ dc 39 b1 600 mv pkCpk centered at C1.3 v @ dc 41 b2 600 mv pkCpk centered at C1.3 v @ dc 42 b3 600 mv pkCpk centered at C1.3 v @ dc 43 b4 600 mv pkCpk centered at C1.3 v @ dc
TQ6122 9 for additional information and latest specifications, see our website: www.triquint.com mixed signal products 0.65 square 0.015 0.060 0.125 0.805 nominal 0.005 top view pin 12 0.035 all dimensions in inches pin 1 0.050 figure 11. mounting footprint figure 10. package dimensions package outline (for reference only) pin 12 pin 23 0.350 0.425 all dimensions in inches pin 34 solder pad 0.050 0.025 pin 1 figure 12. heat-sink mounting arrangement (heat sink not included) thermalloy type 2291c top thermalloy type 2291c base thermal adhesive dac ic use loctite output thermal conductive adhesive (loctite item number 00241) or equivalent to attach heat sink base to ic.
TQ6122 10 for additional information and latest specifications, see our website: www.triquint.com circuit description the TQ6122 dac is based on a current-steering archi- tecture in which weighted currents are switched by an array of differential-pair switches into either the v out or v out output, depending on the state of the input data and blanking bits. essentially, the dac is comprised of six circuit blocks: the input buffer, the data multiplexer, blanking logic, master/slave latch array with segment encode logic, differential-pair switches, and the current source array. (see figure on page 1.) input buffers the input buffers compare the ecl data and control input signals with the eclref level, amplify the differ- ence, and translate this signal to the logic levels used within the ic. by default, the ecl reference is set by an internal generator; however, for best performance and maximum noise margin over temperature, power supply, and device-to-device variations, the user should provide an external level. for general-purpose applications, a simple resistive divider between d gnd and v tt will suffice. for extreme environments or for maximum performance, the eclref level should be slaved to the centerpoint of the incoming data. refer to the digital inputs and terminations discussion later in this document for additional information. note that the data inputs are complemented to indicate that an increasing input value results in the v out level moving more negative. data multiplexer the dac makes provision for accepting data from either of two sources: from a single 8-bit-wide word at the full conversion rate, or from two 8-bit-wide half- speed words which are multiplexed together inside the dac under the control of the sela input. in use, the sela input is set high to select the a-word data and low to select the b-word. it is generally best to use the a-word input when operating the dac unmultiplexed, although the b-word supports full-rate transfers. blanking logic a separate blank input is included to allow the dac to be used in video display applications. when asserted low, the blank input has no effect on the operation of the dac, and the state of the input data words controls the positions of the current switches. when blank is asserted high, however, all internal data bits and the internal blanking bit are synchronously forced high at the next negative-going clock transition, causing the v out output to go to its most negative level. this level is the sum of the normal level associated with an input code of 11111111 plus the increment due to the blanking current being steered away from the v out output to v out . see figure 4 (b). in order to provide more latitude in the timing of the blank signal, the blank input is sampled only when the a-word is selected. when the b-word is selected, the state of the blank input at the time the sela control line goes low is held stable until sela again goes high. in situations where blanking is not used, it is important that the blank input be tied to a solid logic low to prevent accidental assertion of blank = high. note also that when the dac is used in the unmultiplexed mode, the data should be brought in on the a-word inputs, since with sela = low (as would be the case for b-word operation), a transient high level at the blank input would never be cleared and the dac would lock up. the blank_disable pin is normally tied to the v aa rail, allowing i blank to flow to the differential-pair switch and then to the selected output. for applications which do not use blanking, however, the standing offset in the v out output due to the unswitched
TQ6122 11 for additional information and latest specifications, see our website: www.triquint.com mixed signal products blanking current would be undesirable. for cases such as these, the blanking current may be completely turned off by connecting the blank_disable pin to a gnd . master/slave latch with encode logic a nine-wide master latch registers the data coming from the multiplexer and blanking logic. the latch outputs are then split into two groups. the top three bits are trans- lated into a seven-level thermometer code by a binary- to-n-of-seven encoder, while the lower five data bits and the blanking bit are simply delayed. the seven encoder outputs and the six delayed data and blanking bits are re-registered in a slave latch to minimize skew, which, in turn, reduces the glitch impulse. latch timing is set up such that the slave latch is in the sample mode when the input clock is low, meaning that the analog output is updated at the falling edge of the clock. current switches the thermometer code outputs of the slave latch array drive seven switches, each of which steers a current equal to 1/8 of the full-scale step amplitude. the five encoded data bits, on the other hand, switch currents with effective binary weightings from 1/16 of full scale down to 1/128 of full scale. the blanking bit steers a current which is nominally 10.4% of the full-scale amplitude. current-source array the current-source array is the heart of the dac from an analog standpoint, and is responsible for generating the segment, bit, and blanking currents. the maximum full-scale current i fs (less i blank ) is about 45 ma, providing a 1.125 volt maximum swing into the 50- ohm external load. the blanking current is nominally 10.4% of i fs , corresponding to a 10-unit ire blanking interval of 71 mv when the full-scale output is set to 0.679 volt. the i ref current tracks i fs , with a nominal value of 2.5 ma for i fs = 40 ma (i.e., 6.25% of i fs ). figure 13 (a) illustrates the basic circuit of the current- source array, which consists of a set of current sources ranging from the 5 ma segment currents to the binary- weighted current sources for the lower-order bits. the circuit design utilizes source degeneration, averaging, and linear gradient cancellation techniques to obtain matching consistent with up to 10-bit linearity. + v out v out blank diff-pair switch (typical, 15 places) i ref i blank i seg 1 i seg 7 i b4 i b3 i b0 cascodes 2.5 ma (nom) v ref v sense 0.8 v nom, for 1 v f.s. out ext ref. ?5v v aa 2w 3.56w 4w 4w 2w w rs rs rs 2rs 1.77 2 rs 2 v bias (internal) blank rs rlsb figure 13 (a). current-source array circuit v sense -based control method
TQ6122 12 for additional information and latest specifications, see our website: www.triquint.com the absolute value of the current-source array output is determined using an off-chip (silicon) reference generator and op amp in a feedback-loop arrangement. in figure 13 (a), the drop across the source degeneration resistors is compared with the level set by the external reference. under conditions of 1 v peak-to-peak full-scale output swing, the voltage between the v sense and v aa pins of the dac will be in the range of 0.8 v to 1.1 v, with v ref being in the range of 0.7 v to 1.4 v (i.e., v ref may lie above or below v sense by several hundred millivolts). note that, for this control method, the i ref terminal must be connected to ground. an alternative means of controlling the current-source array output is shown in figure 13(b), with the advantage that now the reference current is being sensed after flowing through a path identical to that of the bit and segment currents. thus, any error which may have occurred due to leakage will be directly corrected. here, the v sense pin is left disconnected and the i ref current flows to ground through a stable resistor. the value of the resistor should be chosen to drop about 1 volt under the desired operating conditions, but under no circumstances should the voltage at the i ref pin be allowed to drop below C1.5 v, or the linear relationship between i ref and i fs will be degraded. the primary limitation on the maximum output current is the adjustment range of v sense : if the value of {v sense C v aa } exceeds about 1.2 v, the bottom current- source fets begin to lose headroom by running up against the sources of the cascode transistors, causing the total current to begin limiting, as well as degrading, the linearity. if the designer is willing to accept somewhat degraded linearity and/or slightly higher power dissipation, v aa may be taken down to C6 volts or so, allowing v ref to be adjusted to give {v sense C v aa } a maximum value of about 1.5 v. this translates to an output current of about 50 ma or 1.25 v peak-to- peak into the load. note that under these conditions, the device will not sustain any damage, but full-spec operation of the dac is not guaranteed. figure 13 (b). current-source array circuit i ref -based control method + v out v out blank i ref i blank 2.5 ma (nom) v ref v sense < 1.5 v ext ref. ?5v v aa v bias (internal) blank (n/c)
TQ6122 13 for additional information and latest specifications, see our website: www.triquint.com mixed signal products figure 14. basic dac setup notes: 1. all resistors to v tt are 50-ohm, 1/8 watt, surface-mount, mounted as close to the ic as possible. 2. all v ss and v tt capacitors are rated 3 15 v. all v aa capacitors are rated 3 25 v. 3. use either surface-mount components or keep minimum-length leads on all resistors and capacitors. 4. for best noise isolation, the analog supply (v aa ) and digital supply (v ss ) should connect at only one point, via decoupling networks such as ferrite beads. 5. the input circuitry for b0Cb7, blank, and sela are the same as for a0Ca7. 6. for questions regarding board layout, please contact the factory. iref vaa vref vsense blk.dis. agnd vout vout agnd agnd dgnd vss 1uf 1 m f v plane 50 a5 a4 a3 a2 a1 a0 ext. ecl ref. dgnd ecl ref. 1 m f .01 m f 1000 pf 50 sela blank clk clk 1000 pf b5 b6 b7 + mc1403a v plane v v (v + 2.5 v) mc33071 1uf 2.5 k v v 620 (v +1 v) v v v (i = on) (i = off) z = 50 short microstrip or buried stripline + 1 k adjust for desired full-scale output vss dgnd dgnd vss vss dgnd dgnd note 5 a6 a7 b0 b1 b2 b3 b4 50 note 5 note 5 u = microstrip or other transmission line u u u u u u u u u u u u u u u u u u u u note 5 v aa v aa o out out blank blank cc ee 2.5 k aa aa aa aa out 1 k aa split power supply planes here to minimize noise coupling into analog circuitry. use a common plane for analog and digital grounds. ss v plane ss v plane ss v plane aa l 1 l 2 -5 v supply l , l = fair-rite 2743001111 1 2 v = -5 +0.5 v ss v = -5 +0.25 v aa a7, b7 = msb v plane ss v plane tt v = -2 v tt v plane tt v plane tt 1000 pf .01 m f 1000 pf .01 m f .01 m f 1000 pf 1000 pf .01 m f .01 m f .01 m f 1000 pf application information figure 14 illustrates the basic connection of the dac, showing details for power supplies, data and clock inputs, and outputs terminated in 50-ohm transmission line loads. some issues relating to circuit board layout are also addressed.
TQ6122 14 for additional information and latest specifications, see our website: www.triquint.com power supplies, ground and bypassing to minimize noise coupling, the digital and analog power supplies should be returned to a single-point ground, and power supply buses to the ic should have minimum impedance (power planes are best). the supplies themselves should be well bypassed at high and low frequencies, which requires the use of several different parallel capacitors as shown. the values are not particularly critical; however, due to the fact that a capacitor looks inductive above its self-resonant frequency, one needs to use several different values in parallel, ranging from microfarads to nanofarads, in order to provide adequate wideband bypassing. for best results, use leadless ceramic chip capacitors for bypassing, although leaded components will work satisfactorily if higher noise can be tolerated. a common ground plane has been found to give the best performance. for best results and minimum noise, the digital and analog supplies should be physically separated on the circuit board. when using a common C5 v feed, the v ss and v aa planes should be isolated by ferrite beads (fair-rite p/n 2743001111 or equivalent) as shown in figure 14. using separate lm337mt regulators down- stream of the ferrite beads will provide better isolation. digital inputs and terminations the TQ6122 dac is designed to accept ecl logic levels at all data and control inputs. all ecl inputs, with the exception of the clock (see below), are single-ended and are compared to the ecl threshold reference of C1.3 volts (nominal) in the input buffers of the dac. the ecl reference input equivalent circuit is shown in figure 1. several options are available to the user for externally setting the ecl reference level. the simplest option is that of a voltage divider between d gnd and v tt , setting the ecl termination voltage as shown in figure 15 (a). the nominal value for eclref is C1.3 v; however, due to input offset variations among the input buffers or variations in v tt , some adjustment above or below C1.3 v may give the best results. a good way to settle eclref is to slave the ecl refer- ence level to the center (switching) point of the input data signal. this may be accomplished in two ways: either use the v bb generator output of the device which is generating the ecl signals supplied to the dac, or use an inverter with input and output connected together to generate a level equal to the switching threshold. see figure 15 (b). note that the eclref generator should be able to source and sink up to approximately 5 ma, since the input resistance is about 50 ohms, against an internal C1.3 v (nominal) voltage source. an additional op amp may be used to give more flexibility or more robust drive. see figure 15 (c). figure 15. external ecl reference generator (a) (b) (c) 200 50 v ecl reference input or unused clock (clk) input external ecl inverter 50 (optional op amp) dac input eclref + tt -2 v v tt -2 v
TQ6122 15 for additional information and latest specifications, see our website: www.triquint.com mixed signal products clock input in order to realize the full speed potential of the dac, a clock with an input swing of at least 1 v peak-to-peak, nominally centered on C1.3 v, is required. the clock may be applied in either single-ended or differential fashion. because a differential clock provides maximum speed and best control of the relationship between clock and output transitions, as well as minimum noise, it is the preferred solution. for single-ended clock drive, the customer must drive the unused clock input with an external ecl reference level, which may be generated using a resistive divider or, for best results, an external inverter tied back on itself. see figure 15. input line termination as shown in figure 14, data, control, and clock inputs should be terminated in 50 ohms to v tt , consistent with good ecl practice. for best results, keep terminations physically small surface-mount chip resistors work very well and locate them as close to the ic as possible. the v tt bus should also be locally bypassed to digital ground, using chip capacitors placed close to the terminations. the dac offers good performance for C2.5 v < v tt < C2 v, where the use of v tt < C2 v may allow the designer to eke out the last bit of performance in a noisy or marginal drive-level environment. current-source control loop as illustrated previously in figure 13, and shown in detail in figure 16, the bit current sources are controlled by placing them in a feedback loop which compares the drop across a current-sensing resistor with a stable reference. for nominal 1 volt full-scale output swing, the v ref -to-v aa voltage will be in the 0.8 to 1 v range, and may be derived from a zener or, better still, a bandgap reference such as the 2.5 v motorola mc1403a. the output of the bandgap reference will have to be divided down before being applied to the control op amp, and some means should be provided to trim the output to compensate for v out load resistor variations. the op amp must have input common-mode and output drive ranges which extend down to within at least 0.5 volt of the negative rail for maximum control range. for best noise immunity, both the reference generator and the op amp should share a point connection to the v aa rail, close to the dac. the motorola mc33071 op amp is suitable for this application. standard linear design techniques should be used to minimize thermal drift and offset. note that the temperature coefficient of the nichrome resistors used in the dac is on the order of +6 ppm/ c. figure 16 shows a typical reference control loop circuit. iref vaa vref vsense blk.dis. agnd vout vout agnd agnd dgnd + mc1403a v plane v v (v + 2.5 v) mc33071 1uf 0.01 1000 2.5 k v v 620 (v +1 v) v + 1 k v aa cc ee 2.5 k aa aa aa aa out 1 k aa (i = on) (i = off) v aa blank blank v v out out fig. 16. typical external current-source control loop figure 17 illustrates the relationship between control input v ref and the full-scale output swing. note that the full-scale swing may be reduced below 0.25 v peak-to- peak by pulling v ref below v aa . however, this necessitates a separate negative supply for the control
TQ6122 16 for additional information and latest specifications, see our website: www.triquint.com op amp and reference generator, which may decrease the v aa supply rejection. in circuits which use different negative rails for the dac v aa supply and the op amp, v ref should be clamped to no more than two diode drops below v aa , and a current-limiting resistor should be included at either the op amp output or between its negative supply input and supply input. in the event of turn-on transients and large excursions in the op amp supply before v aa has settled out, these precautions will help prevent breakdown of circuitry within the dac. figure 17. typical v ref -to-v aa transfer characteristics 1.25 1.125 1.00 0.75 0.50 -1.0 0 0.5 1.0 1.25 v out (volts p-p) (maximum recommended) 0.25 v to v (volts) ref aa full-scale output adjust the procedure for setting the full-scale output range is quite straightforward, and involves monitoring the output level(s) using a dvm. with the dac connected to its actual v out and v out load(s), the output is alternately switched between steady state zero- and full-scale levels, and the reference is adjusted until the desired full-scale transition amplitude is obtained. the clock must be running and the blank input set to 0. alternatively, for a dds application, a spectrum analyzer or a power meter may be used to monitor the full-scale output power. blanking current programming the blanking current (i blank in figure 13) is turned off by connecting the blank_disable pin to a gnd to divert the current away from the blank switch and the output of the dac, and turned on by connecting blank_disable to v aa . output equivalent circuit figure 5 illustrates the equivalent circuit of the two dac outputs. each of the bit current sources is switched into either the v out or the v out output, depending on the data stored in the slave latches. a pair of internal 50-ohm resistors are connected from v out and v out to analog ground (a gnd ), and provide reverse termination for the analog output transmission lines. although in principle there is no restriction on the load impedance applied at the outputs, in practice, the best performance will be obtained when driving a 50-ohm terminated transmission line. this is very important from a settling standpoint, since reflections from non- 50-ohm loads will superimpose with new transitions and interfere with settling. the general rule for terminating the outputs is the cleaner, the better. output zero-scale adjust the output baseline, or zero-scale level, may be adjusted by returning the far-end termination resistors to a well-bypassed supply level other than ground. for this general situation, reference figure 5, the instan- taneous output voltages v out and v out are given by: ) C | i out | (r l1 || r t1 ) ) C | i out | (r l2 || r t2 ) v out = v os ( r l1 + r t1 r t1 v out = v os ( r l2 + r t2 r t2 i out = ( digital input 255 ) i fs i out = ( 1 C digital input 255 ) i fs i fs = summation of all individual bit currents digital input = decimal equivalent of the binary input word
TQ6122 17 for additional information and latest specifications, see our website: www.triquint.com mixed signal products disadvantage of requiring a large supply voltage. in general, a 1/8 to 1/4 w carbon-composition resistor with a value of 500 to 1000 ohms will give good performance. keep the lead lengths short when attach- ing to the circuit board and bypass the driven terminal of the resistors with a 1000 pf to 0.01 m f smt (surface- mount) capacitor network to the ground plane. a transistor current source, on the other hand, requires much less power supply overhead, but adds more capacitance to the transmission line. if a transistor is used, it should be a high-f t device with low c cb or c dg ( 0.5 pf, if possible) and installed with short leads. capacitive coupling provides a means of obtaining an output centered on 0 volts. however, simply adding a coupling capacitor at one (or both) of the outputs will cause the dc output level to exceed the C1.5 v output compliance limit. the way to circumvent this problem is to add an offset current between the dac output and the coupling capacitor (as discussed above), or to add a low-loss 50-ohm pad between the dac and the capacitor, as shown in figure 18(b). a t or p attenuator topology is acceptable, having 1 db to 3 db of attenuation. the characteristic impedance must be consistent with the overall system impedance, typically 50 ohms. this approach works, although the lower limit on the output level tends to be very close to the C1.5 v compliance limit for 3 1 v full-scale output swings, so some care and verification will be required. dac 0 volt v 0 volt 50 mimimum-loss pad (1? db) min figure 18(b). ac coupling of outputs figure 18(a). alternate output offset current generators for the case of r l1 = r l2 = r t1 = r t2 = 50 ohms, v os is attenuated by 50%. an overriding factor in setting the output offset is the requirement that v out and v out always remain within the devices output compliance range of C1.5 v to +1 v. note also that in the case of the video application of the dac, the value of the blanking current i blank and the state of the blank input must be included in the expressions for v out and v out . an alternative method of offsetting the output involves injecting an offset current at the output. this may be done using a current source in the form of either a resistor or a transistor as shown in figure 18(a). the resistor has the advantage of minimizing perturbation of the transmission line impedance, with the v os 1000 pf 0.01 uf 500 ?1 k 1/8 ?1/4w carbon comp. 50 ohm r 1 r 2 r 3 v t 50 ohm r e high-f low c device je t short lead short lead note: v min must not exceed the lower output compliance limit of C1.5 v for proper operation. if v min < C1.5 v, decrease the dac output swing by adjusting the v ref drive to the control op amp.
TQ6122 18 for additional information and latest specifications, see our website: www.triquint.com figures 19 through 23 show typical ac performance of the TQ6122. figures 19a and 19b illustrate the response of the dac to an unmultiplexed counter input at 1 gs/s and 1.5 gs/s, respectively. blanking is enabled in both cases. the small glitches appearing at 1/8 of full-scale intervals are shown in more detail in figure 22. figure 19 (a). unmuxed ramp at 1000 ms/s with blanking (guaranteed, 0 to +85 c) figure 19(b). unmuxed ramp at 1500 ms/s with blanking (typical, +25 c) typical ac performance
TQ6122 19 for additional information and latest specifications, see our website: www.triquint.com mixed signal products figure 20(a). muxed ramp at 1000 ms/s with blanking multiplexed behavior is shown in figure 20a and 20b, with a counter input muxed against fixed levels at 1000 ms/s and at 1350 ms/s, respectively. in figure 20a, the ramp is muxed against a steady state mid-scale value, while in figure 20b, the steady state input is 11111111. the apparent droop in the top level in figure 20b is an artifact of the sampler. figures 19a, 19b, and 20a show the effects of blanking, while in figure 20b, the blank input is held low, demonstrating the repetitive nature of the waveform. figure 20(b). muxed ramp at 1350 ms/s with blanking disabled note: in figure 20(a), a0Ca7 are switched, b0Cb6 are low, b7is high and blank is switched. in figure 20(b), a0Ca7 are switched, b0Cb7 are high, and blank is low.
TQ6122 20 for additional information and latest specifications, see our website: www.triquint.com figure 21. typical full-scale transitions at v out and v out (f clk = 1000 mhz) figure 22. typical worst-case glitch impulse (f clk = 1000 mhz) figure 21 illustrates the symmetry of complementary full-scale transitions at v out and v out , while figure 22 depicts a typical worst-case glitch of 6 pv/sec.
TQ6122 21 for additional information and latest specifications, see our website: www.triquint.com mixed signal products figure 23(a). synthesized sine wave output figure 23(a) shows a 1 gs/s, 58.6 mhz sine wave, and figure 23b shows its corresponding spectrum. the spurious-free dynamic range is 46 dbc, a typical value for the device. in figure 23(b), the dac output is attenuated by 6 db going into a spectrum analyzer. figure 23(b). spectrum of a 58.5 mhz sine wave at 1 gs/s
TQ6122 22 for additional information and latest specifications, see our website: www.triquint.com figure 25. chip dimensions, topography, and padout notes: 1. dimensional limits unless otherwise specified: +2 mils ( +51 m m). 2. pins labeled n/c are not connected internally. figure 24. complex modulated sine wave pattern at 1000 mb/s figure 24 shows a modulated sine wave as an example of a more complex waveform. vaa vaa iref ecl ref a0 (lsb) a1 dgnd dgnd dgnd a2 a3 a4 a5 vss vss vss vss clock clock n/c sela dgnd dgnd dgnd blank b7 (msb) b6 b5 vss vss vaa vaa vref vsense blank disable agnd agnd agnd agnd vout vout vout agnd agnd vss vss vss a6 a7 (msb) dgnd dgnd b0 (lsb) b1 dgnd dgnd b2 b3 b4 vss vss vout die size: 129 mils x 111 mils (3110 m m x 2660 m m)
TQ6122 23 for additional information and latest specifications, see our website: www.triquint.com mixed signal products ordering information TQ6122-m 8-bit, 1 gs/s dac in 44-pin package TQ6122-d 8-bit, 1 gs/s dac, die only etf6122 engineering test fixture with 6122 device additional information for latest specifications, additional product information, worldwide sales and distribution locations, and information about triquint: web: www.triquint.com tel: (503) 615-9000 email: sales@tqs.com fax: (503) 615-8900 for technical questions and additional information on specific applications: email: applications@tqs.com the information provided herein is believed to be reliable; triquint assumes no liability for inaccuracies or omissions. triquint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. triquint does not authorize or warrant any triquint product for use in life-support devices and/or systems. copyright ? 1997 triquint semiconductor, inc. all rights reserved. revision 1.0.a october 1997 figure 26. package labelling (44-pin packaged version) see figures 10, 11 and 12 for package dimensions and heat-sink mounting information. 1 tqs usa TQ6122-m yyww xxxx beveled corner component material lead kovar lead plating lead/tin alloy yyww C date code xxxx - lot number

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